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gs8161fz18/32/36bd 18mb flow through synchronous nbt sram 5.5 ns?7.5 ns 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 165-bump bga commercial temp industrial temp rev: 1.00 6/2006 1/28 ? 2006, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? flow through mode ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization ? fully pin-compatible with flow through ntram?, nobl? and zbt? srams ? ieee 1149.1 jtag-compatible boundary scan ? 2.5 v or 3.3 v +10%/?10% core power supply ? lbo pin for linear or interleave burst mode ? pin-compatible with 2m, 4m, and 8m devices ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? zz pin for automatic power-down ? jedec-standard 165- bump fp-bga package ? rohs-compliant 165-bump bga package available functional description the gs8161fz18/32/36bd is an 18mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. because it is a synchronous devi ce, address, data inputs, and read/ write control inputs are ca ptured on the rising edge of the input clock. burst order control ( lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable, zz and output enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's out put drivers off at any time. write cycles are internally self- timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs8161fz18/32/36bd is configured to operate in flow through mode. the gs8161fz18/32/36bdis implemented with gsi's high performance cmos technology and is available in jedec- standard 165-bump fp-bga package. parameter synopsis -5.5 -6.5 -7.5 unit flow through 2-1-1-1 t kq tcycle 5.5 5.5 6.5 6.5 7.5 7.5 ns ns curr (x18) curr (x32/x36) 225 255 200 220 185 205 ma ma
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 2/28 ? 2006, gsi technology 165 bump bga?x18 commom i/o?top view (package d) 1 2 3 4 5 6 7 8 9 10 11 a nc a e1 bb nc e3 cke adv a a a a b nc a e2 nc ba ck w g a a nc b c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpa c d nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa d e nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa e f nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa f g nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa g h nc mch nc v dd v ss v ss v ss v dd nc nc zz h j dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc j k dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc k l dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc l m dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc m n dqpb nc v ddq v ss nc nc nc v ss v ddq nc nc n p nc nc a a tdi a1 tdo a a a nc p r lbo nc a a tms a0 tck a a a a r 11 x 15 bump bga?13 mm x 15 mm body?1.0 mm bump pitch
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 3/28 ? 2006, gsi technology 165 bump bga?x32 common i/o?top view (package d) 1 2 3 4 5 6 7 8 9 10 11 a nc a e1 bc bb e3 cke adv a a nc a b nc a e2 bd ba ck w g a a nc b c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc nc c d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb d e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g h nc mch nc v dd v ss v ss v ss v dd nc nc zz h j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa j k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m n nc nc v ddq v ss nc nc nc v ss v ddq nc nc n p nc nc a a tdi a1 tdo a a a nc p r lbo nc a a tms a0 tck a a a a r 11 x 15 bump bga?13 mm x 15 mm body?1.0 mm bump pitch
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 4/28 ? 2006, gsi technology 165 bump bga?x36 common i/o?top view (package d) 1 2 3 4 5 6 7 8 9 10 11 a nc a e1 bc bb e3 cke adv a a nc a b nc a e2 bd ba ck w g a a nc b c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb c d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb d e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g h nc mch nc v dd v ss v ss v ss v dd nc nc zz h j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa j k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m n dqpd nc v ddq v ss nc nc nc v ss v ddq nc dqpa n p nc nc a a tdi a1 tdo a a a nc p r lbo nc a a tms a0 tck a a a a r 11 x 15 bump bga?13 mm x 15 mm body?1.0 mm bump pitch
gs8161fz18/32/36bd 165-bu mp bga pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs dq a dq b dq c dq d i/o data input and output pins b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq d i/os; active low nc ? no connect ck i clock input signal; active high cke i clock input buffer enable; active low w i write enable; active low e 1 i chip enable; active low e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter adv ance enable; active high zz i sleep mode control; active high lbo i linear burst order mode; active low tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock mch ? must connect high v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 5/28 ? 2006, gsi technology
k 18 sa1 sa0 burst counter lbo adv memory array g ck cke d q nc dqa?dqn k sa1? sa0? d q match write address register 2 write address register 1 write data register 2 write data register 1 k k k k k k sense amps write drivers read, write and data coherency control logic a 0 ?an e 3 e 2 e 1 w b d b c b b b a gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 6/28 ? 2006, gsi technology gs8161fz18/32/36b nbt sram functional block diagram
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 7/28 ? 2006, gsi technology functional details clocking deassertion of the clock enable ( cke ) input blocks the clock input fr om reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observ e clock enable set-up or hold requirem ents will result in erratic operation. flow through mode read and write operations flow through nbt srams are equipped with rising-edge-triggered i nput registers that capture data-i n, address, and control input signals, but do not have a data output register like the one found on pipelined nbt srams. once a read command and an associated read address is clocked into th e ram, the read operation pro ceeds and, if the output enab le pin is driven active low , culminates with the read data appearing on the ram output pins, even if no additional clocks are sent to the ram. a write operation in a flow through nbt sram begins when a write command and write address are clocked into the ram. next, data-in for that write address must be applied to the input pins and held for capture by the very next rising edge of clo ck. a write protocol like the one used on flow through nbt srams?th e capture of the write address and write command on one clock and the capture of the write data-in on the next cl ock?is often described as a late write protocol. it is the combination of the flow through read protocol and th e late write write protocol that allows the flow through nbt sram to achieve seamless back-to-back, r ead-write-read transitions on a bi-directional data bus without requiring the user to insert dead cycles to prevent bus contention during the transition from read to write or write to read.
synchronous truth table operation type address ck cke adv w bx e 1 e 2 e 3 g zz dq notes read cycle, begin burst r external l-h l l h x l h l l l q read cycle, continue burst b next l-h l h x x x x x l l q 1,10 nop/read, begin burst r external l-h l l h x l h l h l high-z 2 dummy read, continue burst b next l-h l h x x x x x h l high-z 1,2,10 write cycle, begin burst w external l-h l l l l l h l x l d 3 write cycle, continue burst b next l-h l h x l x x x x l d 1,3,10 write abort, continue burst b next l-h l h x h x x x x l high-z 1,2,3,10 deselect cycle, power down d none l-h l l x x h x x x l high-z deselect cycle, power down d none l-h l l x x x x h x l high-z deselect cycle, power down d none l-h l l x x x l x x l high-z deselect cycle d none l-h l l l h l h l x l high-z 1 deselect cycle, continue d none l-h l h x x x x x x l high-z 1 sleep mode none x x x x x x x x x h high-z clock edge ignore, stall current l-h h x x x x x x x l - 4 notes: 1. continue burst cycles, whether read or wr ite, use the same control inputs. a deselect continue cycle can only be entered into if a dese - lect cycle is executed first. 2. dummy read and write abort can be considered nops because the sram performs no operation. a write abort occurs when the w pin is sampled low but no byte write pins are active so no writ e operation is performed. 3. g can be wired low to minimize the number of control signals provi ded to the sram. output drivers will automatically turn off du ring write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensur es all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminat ed for all burst continue cycles. gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 8/28 ? 2006, gsi technology
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 9/28 ? 2006, gsi technology high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes: 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for: pipeline and flow through read write control state diagram flow through mode da ta i/o state diagram
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 10/28 ? 2006, gsi technology burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-t o-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementatio ns. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the c ounter generated address to read or write the sram. the starting address for the first cy cle in a burst cycle series is loaded into the sram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin ( lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pi n tied high, interleaved burst se quence is selected. see the tab les below for details. mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst power down control zz l or nc active h standby, i dd = i sb note: there is a pull-down device on the zz pin, so this input pin can be unconnected and the chip will operate in the default stat es as specified in the above table. note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 burst counter sequences bpr 1999.05.18
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 11/28 ? 2006, gsi technology sleep mode during normal operation, zz must be pulled low, either by the user or by it?s intern al pull down resistor. when zz is pulled hi gh, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally after zz recovery time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exitin g sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram tzzr tzzh tzzs tkltkl tkhtkh tkctkc ck zz
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to v dd v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 12/28 ? 2006, gsi technology note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 v dd v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 v dd v notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 13/28 ? 2006, gsi technology v ddq3 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v 1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq i/o input high voltage v ihq 2.0 ? v dd + 0.3 v 1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.8 v 1,3 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. v ddq2 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v 1 v dd input low voltage v il ? 0.3 ? 0.3*v dd v 1 v ddq i/o input high voltage v ihq 0.6*v dd ? v dd + 0.3 v 1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.3*v dd v 1,3 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 0 25 70 c 2 ambient temperature (industrial range versions) t a ? 40 25 85 c 2 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 14/28 ? 2006, gsi technology 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkc v dd + 2.0 v 50% v dd v il capacitance o c, f = 1 mh z , v dd parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 7 pf note: these parameters are sample tested. ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance (t a = 25 = 2.5 v)
dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 15/28 ? 2006, gsi technology
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 16/28 ? 2006, gsi technology operating currents parameter test conditions mode symbol -5.5 -6.5 -7.5 unit 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current device selected; all other inputs v ih o r v il output open (x32/ x36) flow through i dd i ddq 235 20 245 20 205 15 215 15 190 15 200 15 ma (x18) flow through i dd i ddq 215 10 225 10 190 10 200 10 175 10 185 10 ma standby current zz v dd ? 0.2 v ? flow through i sb 40 50 40 50 40 50 ma deselect current device deselected; all other inputs v ih or v il ? flow through i dd 60 65 50 55 50 55 ma notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario. ac electrical characteristics parameter symbol -5.5 -6.5 -7.5 unit min max min max min max flow through clock cycle time tkc 5.5 ? 6.5 ? 7.5 ? ns clock to output valid tkq ? 5.5 ? 6.5 ? 7.5 ns clock to output invalid tkqx 2.0 ? 2.0 ? 2.0 ? ns clock to output in low-z tlz 1 2.0 ? 2.0 ? 2.0 ? ns setup time ts 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.3 ? 1.3 ? 1.5 ? ns clock low time tkl 1.5 ? 1.5 ? 1.7 ? ns clock to output in high-z thz 1 1.5 2.5 1.5 3.0 1.5 3.0 ns g to output valid toe ? 2.5 ? 3.0 ? 3.8 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.5 ? 3.0 ? 3.8 ns zz setup time tzzs 2 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? ns notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recogniz ed on any given clock cycle, zz mu st meet the specified setup a nd hold times as specified above.
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 17/28 ? 2006, gsi technology flow through mode timing (nbt) write a write b write b+1 read c cont read d write e read f write g d(a) d(b) d(b+1) q(c) q(d) d(e) q(f) d(g) tolz toe tohz tkqx tkq tlz thz tkqx tkq tlz th ts th ts th ts th ts th ts th ts th ts tkctkc tkltkl tkhtkh ab c defg *note: e = high(false) if e1 = 1 or e2 = 0 or e3 = 1 ck cke e * adv w bn a0?an dq g jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected.
jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 18/28 ? 2006, gsi technology jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are select ed (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register.
instruction register id code register boundary scan register 0 1 2 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller m* 1 0 control signals * for the value of m, see the bsdl file, which is av ailable at by contacting us at apps@gsitechnology.com . gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 19/28 ? 2006, gsi technology jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents not used gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 20/28 ? 2006, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandator y for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instructi on register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path.
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 21/28 ? 2006, gsi technology sample/preload sample/preload is a standard 1149.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r future use. in this device they replicate the bypass instruction.
jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan re gister between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 22/28 ? 2006, gsi technology
jtag port recommended operat ing conditions and dc characteristics (2 .5/3.3 v version) parameter symbol min. max. unit notes 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v 1 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v 1 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v 1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj 1.7 ? v 5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v 5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v < vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 23/28 ? 2006, gsi technology notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 ? 30pf * jtag port ac test load * distributed test jig capacitance
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 24/28 ? 2006, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns boundary scan (bsdl files) for information regarding the boundary scan chain, or to obta in bsdl files for this part, please contact our applications engineering department at: apps@gsitechnology.com .
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 25/28 ? 2006, gsi technology package dimensions?165-b ump fpbga (package d) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 130.05 150.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.20 c 0.36~0.46 1.40 max.
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 26/28 ? 2006, gsi technology ordering information for gs i synchronous burst rams org part number 1 type package speed 2 (ns) t a 3 status 4 1m x 18 gs8161fz18bd-5.5 flow through 165 bga 5.5 c mp 1m x 18 gs8161fz18bd-6.5 flow through 165 bga 6.5 c mp 1m x 18 gs8161fz18bd-7.5 flow through 165 bga 7.5 c mp 512k x 32 gs8161fz32bd-5.5 flow through 165 bga 5.5 c mp 512k x 32 gs8161fz32bd-6.5 flow through 165 bga 6.5 c mp 512k x 32 gs8161fz32bd-7.5 flow through 165 bga 7.5 c mp 512k x 36 gs8161fz36bd-5.5 flow through 165 bga 5.5 c mp 512k x 36 gs8161fz36bd-6.5 flow through 165 bga 6.5 c mp 512k x 36 gs8161fz36bd-7.5 flow through 165 bga 7.5 c mp 1m x 18 gs8161fz18bd-5.5i flow through 165 bga 5.5 i mp 1m x 18 gs8161fz18bd-6.5i flow through 165 bga 6.5 i mp 1m x 18 gs8161fz18bd-7.5i flow through 165 bga 7.5 i mp 512k x 32 gs8161fz32bd-5.5i flow through 165 bga 5.5 i mp 512k x 32 gs8161fz32bd-6.5i flow through 165 bga 6.5 i mp 512k x 32 gs8161fz32bd-7.5i flow through 165 bga 7.5 i mp 512k x 36 gs8161fz36bd-5.5i flow through 165 bga 5.5 i mp 512k x 36 gs8161fz36bd-6.5i flow through 165 bga 6.5 i mp 512k x 36 gs8161fz36bd-7.5i flow through 165 bga 7.5 i mp 1m x 18 gs8161fz18bgd-5.5 flow through rohs-compliant 165 bga 5.5 c pq 1m x 18 gs8161fz18bgd-6.5 flow through rohs-compliant 165 bga 6.5 c pq 1m x 18 gs8161fz18bgd-7.5 flow through rohs-compliant 165 bga 7.5 c pq 512k x 32 gs8161fz32bgd-5.5 flow through rohs-compliant 165 bga 5.5 c pq 512k x 32 gs8161fz32bgd-6.5 flow through rohs-compliant 165 bga 6.5 c pq 512k x 32 gs8161fz32bgd-7.5 flow through rohs-compliant 165 bga 7.5 c pq 512k x 36 gs8161fz36bgd-5.5 flow through rohs-compliant 165 bga 5.5 c pq 512k x 36 gs8161fz36bgd-6.5 flow through rohs-compliant 165 bga 6.5 c pq 512k x 36 gs8161fz36bgd-7.5 flow through rohs-compliant 165 bga 7.5 c pq 1m x 18 gs8161fz18bgd-5.5i flow through rohs-compliant 165 bga 5.5 i pq 1m x 18 gs8161fz18bgd-6.5i flow through rohs-compliant 165 bga 6.5 i pq notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. mp = mass production. pq = pre-qualification. 5. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 27/28 ? 2006, gsi technology 1m x 18 gs8161fz18bgd-7.5i flow through rohs-compliant 165 bga 7.5 i pq 512k x 32 gs8161fz32bgd-5.5i flow through rohs-compliant 165 bga 5.5 i pq 512k x 32 gs8161fz32bgd-6.5i flow through rohs-compliant 165 bga 6.5 i pq 512k x 32 gs8161fz32bgd-7.5i flow through rohs-compliant 165 bga 7.5 i pq 512k x 36 gs8161fz36bgd-5.5i flow through rohs-compliant 165 bga 5.5 i pq 512k x 36 gs8161fz36bgd-6.5i flow through rohs-compliant 165 bga 6.5 i pq 512k x 36 gs8161fz36bgd-7.5i flow through rohs-compliant 165 bga 7.5 i pq ordering information for gsi sync hronous burst rams (continued) org part number 1 type package speed 2 (ns) t a 3 status 4 notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. mp = mass production. pq = pre-qualification. 5. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
18mb sync sram data sheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 8161fzxxb_r1 ? creation of new datasheet gs8161fz18/32/36bd specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.00 6/2006 28/28 ? 2006, gsi technology

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